Job Requirements

The ideal candidate for this Senior Lead Verification Engineer position should have a strong background in verification methodologies and be able to effectively lead a team in achieving project goals. 10-12 Yrs of work experience, Subsystem Level Verification, Test Plan Writing, Knowledgeable in UVM and System Verilog, Debugging RTL issues, Coverage Writing and SVA Waveform debug using Verdi, Verilog. Must be proficient in IP Verification/SOC Verification and have experience in team leading roles.

Job Id: Aq2i/aQM1U4gq0Jmi6wXkAdDt8Bj/0kvj9P01TJxO0zqatFXa/qP74SteJk7jWaH6uWjNasBaVsOd/4GhRzQr4guIIcAqJvkdnsvAsXSwgsG9PFR0j2YJL8Rw7aQUdQoooAKBrrGvTl2IrgM8yZ69OhwCamdoZ5Wjx3G0pglmparpS7wZwJ2HnAlq8xfq7V9mBR6qSHIajaHnaW4rHUVQo8/t9DB5AL5JZS5xMc9hrI6GnEgzNqhDPQ/KA==